Non-volatile semiconductor memories, such as a split gate flash memory, typically use a stacked floating gate type field effect transistors, in which electrons are induced into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed.
In particular, transistors used in semiconductor memories typically have an oxide-nitride-oxide (ONO) or silicon-oxide-nitride-oxide-silicon (SONOS) stack between the floating gate and control gate in which a single, homogenous nitride or oxynitride layer is used as either a charge storing or retention layer of the memory.
FIG. 1 is a partial cross-sectional view of an intermediate structure for a semiconductor device 100 comprising a SONOS gate stack or structure 102 including a conventional ONO stack 104 formed over a surface 106 of a silicon substrate 108 according to a conventional method. In addition, the device 100 typically further includes one or more diffusion regions 110, such as source and drain regions, aligned to the gate stack and separated by a channel region 112. Briefly, the SONOS structure 102 includes a poly-silicon (poly) gate layer 114 formed upon and in contact with the ONO stack 104. The poly gate 114 is separated or electrically isolated from the substrate 108 by the ONO stack 104. The ONO stack 104 generally includes a lower oxide layer 116, a nitride or oxynitride layer 118 which serves as a charge storing or memory layer for the device 100, and a top, high-temperature oxide (HTO) layer 120 overlying the nitride or oxynitride layer.
One problem with conventional ONO and SONOS structures 102 and methods of forming the same is the single, homogenous nitride or oxynitride layer 118 that is used as a charge retention or memory layer, and which can have poor or decreasing data retention over time, limiting the device 100 lifetime and/or its use in several applications due to leakage current through the layer. Referring to FIG. 2A, if the memory layer is silicon (Si) rich there is a large, initial window or difference between the programming voltage (VTP), represented by graph or line 202, and the erase voltage (VTE), represented by line 204, but the window collapse very rapidly in retention mode to an end of life (EOL 206) of about 1.E+07 seconds.
Referring to FIG. 2B, if on the other hand the memory layer is if a high quality nitride layer, that is one having a low stoichiometric concentration of Si, the rate of collapse of the window or Vt slope in retention mode is reduced, but the initial program-erase window is also reduced. Moreover, the slope of Vt in retention mode is still appreciably steep and the leakage path is not sufficiently minimized to significantly improve data retention, thus EOL 206 is only moderately improved.
Another problem with the conventional approach to forming an ONO structure is that when a pure oxide layer is used as a tunnel bottom oxide the oxide layer needs to be thin enough to allow the initial program-erase window to be large to support an end of life program-erase window sufficient to meet a specified minimum difference between VTP an VTE. On the other hand, a tunnel oxide layer that is too thin will limit the retention by creating a charge loss path from the memory layer to the substrate that is too small or short, resulting in a bigger or steeper slope of Vt in retention mode.
Accordingly, there is a need for a memory device including an ONO stack with an oxynitride layer as a memory layer that exhibits improved data retention and methods of forming the same. It is further desirable that ONO stack and method not adversely impact programming and erase speed.